The present invention generally relates to basic cells of gate array devices, and in particular to improvements in a relationship between source/drain diffusion regions and electrode contact holes formed in insulating films formed on the diffusion regions.
A gate array device is an integrated circuit device formed on a a semiconductor chip on which a plurality of basic cells, which are formed by a production process common to all gate array devices, are arranged in the form of matrix. Each basic cell is configured by transistors, diodes, resistors and so on. An interconnecting (or wiring) process is carried out for the basic cells to build desired logic elements and circuits in accordance with designers, specifications.
Most conventional gate array devices are configured by complementary metal oxide semiconductor (hereafter simply referred to as CMOS) transistors. The gate array device of this type is known as a CMOS gate array device. Each of the basic cells contains an n-channel element region and a p-channel element region. For example, the n-channel element region has a p-type well region formed in an n-type silicon substrate. In the p-type well region, there are formed n.sup.+ -type diffusion regions which are source/drain (hereafter simply referred to as S/D) regions. The n.sup.+ -type diffusion regions related to one basic cell are located between adjacent p.sup.+ -type substrate contact regions formed in the p-type well region. One or more gate electrodes are arranged on a gate insulating film and between the adjacent S/D diffusion regions. On the other hand, p.sup.+ -type diffusion regions related to one basic cell are formed in the n-type silicon substrate, and are located between adjacent n.sup.+ -type substrate contact regions formed in the n-type substrate. The gate electrodes are provided on the gate insulating film and between the adjacent S/D diffusion regions.
The S/D regions and the substrate contact regions may be coupled with each other to form desired elements such as CMOS inverters and to make a substrate contact for coupling the S/D regions with the substrate. Conventionally, a plurality of interconnecting (wiring) channels on which interconnecting lines are arranged, are provided for each basic cell. These interconnecting channels extend in a direction of a column composed of basic cells. Actually, the interconnecting lines are laid on an insulating film deposited on the S/D diffusion regions and the gate electrodes. The interconnecting lines mutually connect the S/D regions and substrate contact regions through contact holes formed in the insulating film deposited thereon. The contact holes are filled with material forming the interconnecting lines. The contact holes are formed at predetermined positions on the S/D regions and the substrate contact regions.
However, the conventional basic cells of the gate array device of the above structure have the following disadvantages. As is known, it is very difficult to accurately form the contact holes at predetermined positions. In other words, it is frequently observed that the contact holes are formed in a state where they deviate from the predetermined positions. For example, when contact holes for making the electric contact with the S/D diffusion regions adjacent to the substrate contact regions are formed partially beyond the S/D diffusion regions, a surface portion of the substrate becomes exposed through the contact holes. In this case, when an interconnecting line which is not designed to be coupled with the substrate contact region is provided over the above contact holes, a short circuit occurs between the exposed substrate surface portion and the above S/D diffusion region via the interconnecting line. This problem becomes greater as the integration density increases. In order to prevent the short circuit, a compensated impurity diffusing process must be carried out for the exposed surface portion of the substrate. However, the compensated impurity diffusing process is complex and cumbersome, and takes a long time, because it consists of steps for masking, ion implantation, removal of the resist film, and annealing.
In addition, the conventional basic cell is designed so that the substrate contact can be built by using any one of the plurality of interconnecting channels. For this purpose, the substrate contact regions are formed so as to have the width sufficient to form contact holes at any positions thereof. This prevents an increased integration density from being obtained.